A VLSI Architecture for Soft-Output PR4 Detection
نویسندگان
چکیده
A 0.35 m 3-level metal CMOS ASIC is developed for forward-backward soft-output detection of Class-IV partial response signaling. The novel, low-complexity architecture uses a difference metric and a computational kernel implemented as a limiter. The chip was verified to operate at 20 MHz (20 Mbps), the highest speed of our IC tester. Simulations predict operation of up to 150 Mbps.
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تاریخ انتشار 2000